IP core of high-speed multi-channel data acquisiti

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IP core design of high-speed multi-channel data acquisition controller based on FPGA Abstract This paper introduces the IP core design of multi-channel high-speed data acquisition module controller based on FPGA embedded system. Using TI's 6-channel synchronous acquisition A/D converter (ADS8364), the IP core is designed by using hardware description language to process the collected data. At the same time, the interface between the IP core and the embedded system is designed. In the ISE development tool of Xilinx company, the hard FIFO controller in FPGA device is used to assist in the design of IP core, and the embedded development tool EDK is used to establish the FPGA embedded system, and the user-defined IP core is added and modified. The effectiveness of this method is verified by simulation

key words FPGA data acquisition ADS8364 IP core fifo

with the continuous progress and development of programmable logic devices, FPGA is playing a more and more important role in embedded systems. The IP core of the controller of the signal acquisition module in the power quality monitoring system introduced in this paper is implemented by hardware description language. Firstly, it takes ADS8364 chip as the control object, and stores the 6-channel synchronous sampling 16 bit data to the FIFO controller in combination with the actual circuit. When FIFO controller stores one cycle of data, it generates an interrupt signal, which is read by PowerPC at high speed. This can reduce the burden on the CPU. It does not need to frequently read the 6-channel sampling data, saving CPU computing resources

1 principle and specific application of ADS8364 chip ADS8364 is a 16 bit a/D conversion chip with high speed, low power consumption and 6 channels (three-phase voltage and three-phase current) synchronous sampling designed for high-speed synchronous data acquisition system by TI company. Analog and digital power supply are adopted respectively. At the analog input end, there are analog reference voltage input, output pin and signal six channel positive and negative input pin; In the digital terminal, it mainly includes controlling the read/write, reset of ADS8364, chip selection pin and conversion result output bus with key technology as a breakthrough in the new chemical material industry

ads8364 chip conversion process: when the holdx of ADS8364 maintains a low level of at least 20 ns, the conversion starts. After the conversion result is stored in the output register, the output of pin EOC will maintain the low level of half a clock cycle to prompt the data analysis processor to receive the conversion result. The processor can read out the data through the parallel output bus by setting RD and CS as low level. In the process of receiving converted data, the timing of each pin of ADS8364 chip can be coordinated to ensure the good operation of the monitoring equipment. The specific timing arrangement is shown in Figure 1

ads8364 chip's data output mode is controlled by byte, add and address lines A2, A1 and A0 respectively. The reading mode of conversion results is determined by the data analysis processor used in the power quality monitoring system. Generally, any one of direct reading, cyclic reading and FIFO mode can be used. If byte is 0 or 1, the data bits obtained during each reading can be determined. If add is 0 or 1, the channel address information or channel A/D conversion result can be determined for the first reading. In practical application, we combine the ability of six 16 bit ADCs in ADS8364 analog-to-digital converter to work synchronously in pairs. Three hold signals (holda, holdb, holdc) can be gated at the same time, and the conversion results will be saved in six registers. For each read operation, ADS8364 outputs 16 bit data, and the highest bit is the symbol bit. According to the working sequence of ADS8364 cyclic reading mode shown in Figure 2, it is necessary to set byte to 0, A2, A1 and A0 to 1, 1 and 0 respectively

2.3 design of a/D conversion chip control module and top-level file

design of controller module:

① according to the working principle of ADS8364: holdx maintains a low level of at least 20ns, and the conversion starts, so the controller needs to generate a hold cycle signal according to the timing requirements

② after the conversion, according to the response state of EOC, it is necessary to set RD and CS as low level, so that the data can be read out through the parallel output bus. The following is the Verilog description of changing Rd value according to the state of EOC:

according to the working sequence in Figure 1 and the cyclic reading mode in Figure 2, as well as the requirements for data acquisition frequency (12.8 kHz can detect the yield strength, tensile (compression, bending) strength, elongation, non proportional strength, elastic modulus and other parameters of the material), control the corresponding pins of the chip, and connect them with FIFO so that the collected data can be written into FIFO in a cyclic manner. Verilog hardware description language is used to realize the above functions, and the top-level file is established to correctly connect each functional module

the Verilog of the top-level file is described as follows:

as shown in Figure 3, the output of the clock frequency division part and the FIFO data are written to the clock and ad_ The clock of Ctrl is connected with the clock of a/D conversion chip. AD_ The CTRL part mainly controls the ADS8364 chip. The output RD is also connected to the FIFO write enable end to control the FIFO data writing. The read clock of FIFO is connected to the system clock, so the flexible packaging manufacturer basically does not need CPU control. When FIFO writes data of one cycle, prog_ Full generates an interrupt signal, and the CPU responds and reads the FIFO

2.4 simulation

synthesize the top-level files and simulate them in mode lsim. The simulation results of the data acquisition controller are shown in Figure 4. When holdx_ N refers to low level, start a/D conversion, and then according to EOC_ N generates 6 RDS_ N low level signal, reading data circularly. When the FIFO stores data for one cycle, the CPU sets the read enable port of the FIFO to high level and reads the data in the FIFO at a high speed. If the data in FIFO is empty, em10 Displacement resolution: 0.01mmpty is high level

3 use Xilinx embedded development tool EDK to design IP core

embedded development software EDK provides designers with automatic design wizard base system builder (BSB), which can guide engineers to quickly complete the whole design process. Create a project using BSB. After the project is created, add a user-defined IP core using the CIP (create and import peripheral wizard) provided by EDK. The generated user IP is saved in the pcore folder under the EDK project directory. The user IP core directory is shown in Figure 5

the folder data is used to store user IP configuration files, such as.Prj files,.Mpd files, and.Pao files; The folder HDL is used to store the HDL code of the user IP, that is.V or.Vhd files; The project in the devl (simmodels) folder can enable users to design, synthesize and simulate the project on the ISE platform. If the design needs to add a table, it can be placed in the netlist folder. CIP uses a special interface specification (ipif) when establishing the user IP core. Ipif is a highly parameterized custom interface verified and optimized. It provides a simplified bus protocol IPIC (IP interconnect). It is much simpler to operate this bus than to directly operate PLB and OPB. Through ipif module, its parametric customization can meet the design requirements, which will reduce the workload of design and testing. Copy the designed Verilog file to the corresponding HDL folder under the IP core directory, start the ISE development platform and open the project file in the devl folder. The structure displayed in sources for implementation is shown in Figure 6. In the figure, adsfifo.vhd is the description file of IPIC, and user logic.v (or useru logic.vhd) can realize the function design of user IP core. It is necessary to add necessary Port declaration and logic design to adsfifo.vhd to make PLB controller and user IP Design port connect accordingly. After the design is completed, the IP core is integrated and simulated in ISE platform. After synthesis, check the resource usage of FPGA devices, as listed in Table 1

modify the user as needed_ Logic.v (or user logic.vhd), add Port declaration and logical design to it:

note: after integration, you need to use the CIP tool in EDK to re import the user IP core. During the import process, you need to specify the MPD configuration file and XST project file (*.pfj) file, so that CIP can automatically add the associated.V or.Vhd file. After importing, you can see the user IP core in the project local pcores category of EDK's ipcatalog. You can add this IP core to the EDK project, set its bus interface, port and addresses, generate a bitstream file, and download it to the development board for debugging

4 summary

the IP core of data acquisition designed by FPGA and ADS8364 has simple interface, high acquisition accuracy, can collect multiple signals at the same time, and can reduce the burden of CPU in FPGA embedded system and save CPU computing resources. Through simulation and downloading to the development board, the design can meet the requirements of high precision and high real-time for high-speed alternating voltage signal acquisition

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